This application claims the priority of Korean Patent Application No. 2003-100549, filed on Dec. 30, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to set programming methods for a phase-change memory array and write driver circuits which may carry out the set programming method.
2. Description of the Related Art
A PRAM (Phase-change Random Access Memory) is a non-volatile memory device which may store data using a material, for example, GST (Ge—Sb—Te), with a resistance which may vary in response to a phase change of the material which may be caused by a temperature variation. The material may be referred to as a phase-change material.
During a writing operation in a PRAM device, the phase-change material may change state to a crystalline state or an amorphous state when a current may flow through. The transition to the crystalline state or amorphous state of the phase-change material may depend on the intensity and/or quantity of the current flowing through the phase-change material. A larger quantity of current may flow through the phase-change material for a period of time, and the phase-change material may change into the amorphous state, which may be referred to as a reset state. The reset state may correspond to data 1.
A current less than the reset current may flow through the phase-change material for a period of time, and the phase-change material may transform into a crystalline state, which may be referred to as a set state. The set state may correspond to data 0.
The resistance of the phase-change material in the reset state may be greater than the resistance in the set-state. A memory cell may transition from the set state to the reset state by passing a reset current through the phase-change material, which may heat the phase-change material to a temperature greater than a melting temperature and the phase-change material may be cooled (for example, rapidly).
A memory cell may be changed from the reset state into the set state by passing a set current through the phase-change material which may heat the phase-change material to a temperature greater than a crystallization temperature and may be kept in this state for an amount of time and the phase-change material may be cooled.
FIG. 1 is a graph illustrating examples of current pulses for writing data to the phase-change material. Referring to FIG. 1, a larger current pulse with a reduced period may be applied to and may melt the phase-change material. The phase-change material may be cooled (for example, rapidly) and the phase-change material may transform to the amorphous state (for example, reset state). A small current pulse with a long period may be applied to the phase-change material, which may heat the phase change material to a crystallization temperature or higher, to change the phase-change material to a crystalline state (set state).
In a memory array which may include a plurality of phase-change memory cells, the memory cells may include different parasitic loadings according to arrangements in a memory array. Signal lines which may be connected to the memory cells may have different loads. A reset current difference among the memory cells may be generated during a fabrication process as the area of the memory array may increase. The reset current difference may result in a set current difference. Some of the memory cells may not change to the set state with one set current.
For example, some of the memory cells may change to the set state in response to a set current and some of the memory cells may not change to a set state in response to a set current. This may result in the phase-change memory array to malfunction.